FPGA IP cores
Aphesa's IP core for imaging are primarily used in Aphesa custom and standard cameras and were originally developed for Xilinx FPGA, most often Xilinx Spartan 6.
These algorithms are also offered as IP cores (closed sources) and can be tailored to the customer needs. We also have experience with Lattice and Altera FPGAs as well as other FPGAs from the Xilinx family, including Kintex7, Artix7 and Spartan3, although not all algorithms work on these FPGAs as is.
Aphesa is a Xilinx Associate member.
Automatic gain and exposure control
Based on calculated image statistics from frames N-M...N-1, the algorithm will calculate the required gain and exposure time for frane N.
This cores is a pass-though for the image and provides two parallel output busses with relative exposure and gain values that can then be used by the main code to program the sensor for its next frame.
The user can set a maximum exposure, a maximum gain, a change period, an averaging filter over time, up to two independent regions of interest with weighted gain and a background with 16 tiles of weighted interest. The user can also specify an exposure compensation target and a saturation limit.
This core only requires cells (gates and flip-flops and a small BRAM FIFO), it does not require external memory. The core has a small latency but no bandwidth limitation for reasonable image data rates.
The core is compatible with monochrome and color sensors as the input format can be either raw data of a monochrome sensor or RGB parallel data or YCC type of data.
Automatic dynamic range, gain and exposure control
This is a more advanced version of the previous IP core for image sensors with high dynamic range modes. The core will work with image sensors with dual gain, dual exposure or piecewise linear response (multi-slope HDR response) with up to 5 kneepoints.
This version of the core also requires the user to specify maximum image-to-image ratio in order to avoid dynamic range gaps (SNR holes) and an additional parameter called saturation limit. The algorithm has additional output data for senor configuration, the format depends on the version of the core instantiated. It is also compatible with color sensors.
This core requires more gates and flip-flops than the standard version but not more memory and does not have additional latency.
Based on statistical data from previous frames (at least one), the required global tone mapping function for the next frame is calculated in order to maximize image contrast by equalizing the histogram. The core can be used on live image data or data from memory in order to apply the mapping directly on the image from which the statistical parameters are calculated.
This core only requires gates and flip-flops and a small BRAM FIFO.
The core can generate the reference DSNU image and store it in external RAM and/or flash and then use this image as the reference image to compensate DSNU of live images.
This core requires gates, flip-flops and FIFOs and also requires extensive access to external memory for burst reads during normal operation or burst reads and writes during the calculation of the reference image.
A more advanced version of the previous algorithm that can generate DSNU and PRNU images and compensate for both DSNU and PRNU. The core requires twice more size and twice the memory bandwidth.
At the same time as correcting for PRNU, the algorithm can also correct for lens shade and cosine fall-off based on radial parameters and principal point coordinates.
Other IP codes
- 3x3 bayer pattern demosaicing
- 5x5 edge preserving bayer pattern demosaicing
- Color correction matrix / color space conversion matrix
- Gamma correction / user programmable global tone mapping with LUT
- Generic 3x3 or 5x5 matrix based filtering
- Edge enhancement